The present invention relates to a memory device and method of fabricating the same, and more particularly, to forming a boundary region between cell and peripheral regions in the memory device.
In the memory device, e.g., the NAND flash, the pitch of the isolation trench is becoming smaller and smaller as the technology advances. The isolation trench is gap-filled with an oxide film to form field oxide structure (FOX) or isolation structure. Such an oxide film is typically formed using High Density Plasma (HDP) method. The step-coverage failure of the isolation structure is more likely to occur as the isolation trench is provided with a smaller pitch.
The step-coverage failure in the memory cell region can be quite serious. The step-coverage failure may generate a void in the isolation structure of the memory cell that can affect the reliability of the memory cell. To address this concern, the depth of an isolation trench of the memory cell region is set to 2000 Å or less in order to improve the step coverage.
However, the depth of the isolation trench at the peripheral region tends to be substantially deeper. That is, the voltage applied to the peripheral components of the device generally has not changed even as the technological advance has greatly reduced the size of the device. Accordingly, a transistor formed in the peripheral region continues to be provided with a deep isolation trench to withstand a high voltage of 20V or more.
Currently a boundary region between the cell region and the peripheral region is defined by forming an active region or forming an isolation layer. If the active region is formed, a gate oxide layer thinning phenomenon may occur at an edge of the active region. If a high voltage of about 20V is applied to the gate line during a NAND flash memory device operation, the gate oxide breakdown could occur at the thinned-out portion of the gate oxide layer. This would result in device failure.